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| rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. adf7011 high performance ism band ask/fsk/gfsk transmitter ic features single chip low power uhf transmitter frequency band 433 mhz to 435 mhz 868 mhz to 870 mhz on-chip vco and fractional-n pll 2.3 v to 3.6 v supply voltage programmable output power ?6 dbm to +12 dbm, 0.3 db steps data rates up to 76.8 kbps low current consumption 29 ma at +10 dbm at 433.92 mhz power-down mode (<1 a) 24-lead tssop package hooks to external vco for < 1.4 ghz operation applications low cost wireless data transfer wireless metering remote control/security systems keyless entry functional block diagram general description the adf7011 is a low power ook/ask/fsk/gfsk uhf transmitter designed for use in ism band systems. it contains and integrated vco and - ? fractional-n pll. the output power, channel spacing, and output frequency are program- mable with four 24-b it registers. t he fractional-n pll enables the user to select any channel frequency within the european 433 mhz and 868 mhz bands, allowing the use of the adf7011 in frequency hopping systems. the fractional-n also allows the transmitter to operate in the less congested sub-bands of the 868 mhz to 870 mhz srd band. it is possible to choose from the four different modulation schemes: binary or gaussian frequency shift keying (fsk/ gfsk), amplitude shift keying (ask), or on/off keying (ook). the device also features a crystal compensation register that can provide 1 ppm resolution in the output frequency. indirect temperature compensation of the crystal can be accom- plished inexpensively using this register. control of the four on-chip registers is via a simple 3-wire inter- face. the devices operate with a power supply ranging from 2.3 v to 3.6 v and can be powered down when not in use. vco ook/ask ldo regulator muxout lock detect serial interface frequency compensation center frequency fractional-n sigma-delta ook/ask pfd/ charge pump r clk pa fsk/gfsk osc1 osc2 clk out cpv dd cp gnd c reg c vco vco gnd v dd rf out rf gnd c reg r set muxout test a gnd ce clk data le txdata txclk d gnd dv dd cp out vco in adf7011
rev. 0 ? adf7011?pecifications 1 (v dd = 2.3 v to 3.6 v, gnd = 0 v, t a = t min to t max , unless otherwise noted. typical specifications are at v dd = 3 v, t a = 25 c, fpfd = 4 mhz @ 433 mhz, fpfd = 22.1184/5.) parameter min typ max unit rf characteristics output frequency ranges lower srd band 433 435 mhz upper srd band 868 870 mhz phase frequency detector frequency 3.4 20 mhz transmission parameters transmit rate 2 fsk 0.3 76.8 kbits/s ask 0.3 9.6 kbits/s gfsk 0.3 76.8 kbits/s frequency shift keying fsk separation 3 1 110 khz using 3.625 mhz pfd 4.88 620 khz using 20 mhz pfd gaussian filter t 0.5 amplitude shift keying depth 28 db on/off keying 40 db output power (no filtering) 4 868 mhz 3 dbm 433 mhz 10 dbm output power variation max power setting 9 12 dbm v dd = 3.6 v max power setting 11 dbm v dd = 3.0 v max power setting 9.5 dbm v dd = 2.3 v programmable step size ?6 dbm to +12 dbm 0.3125 db logic inputs v inh , input high voltage 0.7 v dd v v inl , input low voltage 0.2 v dd v i inh /i inl , input current 1 a c in , input capacitance 10 pf control clock input 50 mhz logic outputs v oh , output high voltage dv dd ?0.4 v, i oh = 500 a v ol , output low voltage 0.4 v, i ol = 500 a clk out rise/fall time 16 ns f clk = 4.8 mhz into 10 pf clk out mark: space ratio 50:50 power supplies voltage supply dv dd 2.3 3.6 v transmit current consumption 433 mhz 0 dbm (1 mw) 17 ma 10 dbm (10 mw) 29 ma 868 mhz 0 dbm (1 mw) 19 ma 3 dbm (2 mw) 20.5 ma 10 dbm (10 mw) 34 ma crystal oscillator block current consumption 190 a regulator current consumption 280 a power-down mode low power sleep mode 0.2 1 a rev. 0 adf7011 e3e parameter min typ max unit phase-locked loop vco gain 433 mhz/868 mhz 40/80 mhz/v @ 868 mhz phase noise (in-band) 5 433 mhz e81 dbc/hz @ 5 khz offset phase noise (out-of-band) 6 e90 dbc/hz @ 1 mhz offset phase noise (in-band) 7 868 mhz e83 dbc/hz @ 5 khz offset phase noise (out-of-band) 8 e95 dbc/hz @ 1 mhz offset 100 khz loop bw spurious 9, 10 47e74, 87.5e118, 174e230, 470e862 mhz e54 dbm 9 khz e 1 ghz e36 dbm above 1 ghz e30 dbm. assumes external harmonic filter. harmonics 10 second harmonic, 433 mhz/868 mhz e23/e28 e20/e23 dbc third harmonic, 433 mhz/868 mhz e25/e29 e22/e25 dbc other harmonics, 433 mhz/868 mhz e26/e40 e23/e35 dbc reference input crystal reference 433 mhz 1.7 22.1184 mhz 868 mhz 3.4 22.1184 mhz external oscillator frequency 3.4 40 mhz input level, high voltage 0.7 v dd v input level, low voltage 0.2 v dd v frequency compensation pull in range of register 1 100 ppm pa characteristics rf output impedance 868 mhz 16 e j33 m = mod control. 4 the output power is limited by the spurious requirements of etsi at +55 rev. 0 ? adf7011 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adf7011 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1, 2 (t a = 25 c, unless otherwise noted.) v dd to gnd 3 . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to + 7 v cpv dd to gnd . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to + 7 v digital i/o voltage to gnd . . . . . . . ?.3 v to dv dd + 0.3 v operating temperature range industrial (b version) . . . . . . . . . . . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . . ?5 c to +125 c maximum junction temperature . . . . . . . . . . . . . . . . . 125 c tssop ja thermal impedance . . . . . . . . . . . . . . 150.4 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 235 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 c ordering guide temperature model range package option adf7011bru ?0? to +85? ru-24 (tssop) adf7011bru-reel ?0? to +85? ru-24 (tssop) adf7011bru-reel7 ?0? to +85? ru-24 (tssop) (v dd = 3 v 10%; vgnd = 0 v, t a = 25 c, unless otherwise noted.) timing characteristics limit at t min to t max parameter (b version) unit test conditions/comments t 1 10 ns min data to clock setup time t 2 10 ns min data to clock hold time t 3 25 ns min clock high duration t 4 25 ns min clock low duration t 5 10 ns min clock to le setup time t 6 20 ns min le pulsewidth guaranteed by design but not production tested. specifications subject to change without notice. clock db23 (msb) db22 db2 db1 (control bit c2) data le db0 (lsb) (control bit c1) t 6 t 1 t 2 t 3 t 4 t 5 figure 1. timing diagram notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 this device is a high performance rf integrated circuit with an esd rating of <1 kv and is esd sensitive. proper precautions should be taken for handling and assembly. 3 gnd = vcognd = cpgnd = rfgnd = dgnd = agnd = 0 v. rev. 0 adf7011 e5e pin configuration top view (not to scale) 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 tssop adf7011 d gnd muxout txclk txdata le r set cpv dd cp gnd cp out clk ce clk out osc2 osc1 vco gnd test c reg c vco vco in a gnd dv dd rf gnd rf out data pin function descriptions pin no. mnemonic function 1r set external resistor to set change pump current and some internal bias currents. use 4.7 k as default: i r cp max set = 95 . so, with r set = 4.7 k , i cp max = 2.02 ma. 2 cpv dd charge pump supply. this should be biased at the same level as rf out and dv dd . the pin should be decoupled with a 0.1 f capacitor as close to the pin as possible. 3cp gnd charge pump ground. 4cp out charge pump output. this output generates current pulses that are integrated in the loop filter. the integrated current changes the control voltage on the input to the vco. 5c ec hip enable. a logic low applied to this pin powers down the part. this must be high for the part to function. this is the only way to power down the regulator circuit. 6 data serial data input. the serial data is loaded msb first with the two lsbs being the control bits. this is a high impedance cmos input. 7 clk serial clock input. this serial clock is used to clock in the serial data to the registers. the data is latched into the 24-bit shift register on the clk rising edge. this input is a high impedance cmos input. 8l el oad enable, cmos input. when le goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. 9 txdata digital data to be transmitted is input on this pin. 10 txclk gfsk only. this clock output is used to synchronize microcontroller data to the txdata pin of the adf7011. the clock is provided at the same frequency as the data rate. 11 muxout this multiplexer output allows either the digital lock detect (most common), the scaled rf, or the scaled reference frequency to be accessed externally. used commonly for system debug. see the function regis- ter map. 12 d gnd ground pin for the rf digital circuitry. 13 clk out the divided down crystal reference with 50:50 mark-space ratio. may be used to drive the clock input of a microcontroller. to reduce spurious components in the output spectrum, the sharp edges can be reduced with a series rc. for 4.8 mhz output clock, a series 50 into 10 pf will reduce spurs to < e 50 dbc. defaults on power-up to divide by 16. 14 osc2 oscillator pin. if a single-ended reference (such as a tcxo) is used, it should be applied to this pin. when using an external signal generator, a 51 resistor should be tied from this pin to ground. the xoe rev. 0 e6e adf7011 pin function descriptions (continued) pin no. mnemonic function 15 osc1 oscillator pin. for use with crystal reference only. this is three-stated when an external reference oscilla- tor is used. 16 vco gnd voltage controlled oscillator ground. 17 test input to the rf fractional-n divider. this pin allows the user to connect an external vco to the part. disabling the internal vco activates this pin. if the internal vco is used, this pin should be grounded. 18 dv dd positive supply for the digital circuitry. this must be between 2.3 v and 3.6 v. decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. 19 rf gnd ground for output stage of transmitter. 20 rf out the modulated signal is available at this pin. output power levels are from e16 dbm to +12 dbm. the output should be impedance matched to the desired load using suitable components. see the rf output stage section. 21 a gnd ground pin for the rf analog circuitry. 22 vco in the tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (vco). the higher the tuning voltage, the higher the output frequency. 23 c vco a 0.22 f capacitor should be added to reduce noise on vco bias lines. tied to the c reg pin. 24 c reg a 2.2 f capacitor should be added at c reg , tied to gnd, to reduce regulator noise and improve stability. a reduced capacitor will improve regulator power-on time but may cause higher spurious components. rev. 0 t ypical performance characteristicseadf7011 e7e rl = 10.0dbm v dd = 3v pfd frequency = 19.2mhz loop bw = 100khz rbw = 1khz 868.3mhz span 5.000mhz tpc 1. fsk modulated signal, f deviation = 58 khz, data rate = 19.2 kbps, 10 dbm rl = 10.0dbm v dd = 3v pfd frequency = 19.2mhz loop bw = 1mhz rbw = 3khz 868.3mhz span 500khz e2dbm e36dbm @ 200khz tpc 2. ook modulated signal, data rate = 4.8 kbps, 4 dbm start 800mhz stop 7.750ghz + 10dbm second harmonic e22dbc third harmonic e34dbc rbw 1.0mhz tpc 3. harmonic levels at 10 dbm output power. see figure 15. 30.00 s 851.000mhz 868.000mhz 885.000mhz 5.00 s e20.00 s 5.00 s/div v dd = 3v pfd frequency = 19.2mhz loop bw = 100khz tpc 4. pll settling time, 852 mhz to 878 mhz, 23 rev. 0 e8e adf7011 ch1 500mv c1 freq 1.6mhz m 200ns c1 rise 144.8ns c1 fall 145.6ns c1 +duty 49.385% tpc 7. 1.6 mhz clock out waveform span 5.00mhz 868.3mhz + 10dbm v dd = 3v pfd frequency = 19.2mhz loop bw = 100khz rbw = 10hz +1.6mhz e53dbc tpc 8. spurious signal generated by clock out 0.8 0.9 1.0 1.1 1.2 1.3 1.4 frequency (ghz) 0 e5 e10 e15 e20 e25 sensitivity (dbm) tpc 9. n-divider input sensitivity frequency (mhz) 90 80 885 gain (mhz/v) 70 60 945 925 915 905 895 50 40 100 110 935 v dd = 3v t a = 25 c tpc 10. typical vco gain pa setting (modulation register) 40 level (dbm) e30 v dd = 2.2v v dd = 3.0v v dd = 3.6v e25 e20 e15 e10 e5 0 5 10 15 20 60 80 100 120 mid range low range high range tpc 11. pa output programmability, t a = 25 c supply voltage (v) 40 38 2.2 current (ma) 36 34 3.4 3.0 2.8 2.6 2.4 32 30 42 44 3.2 3.6 tpc 12. i dd vs. v dd @ 10 dbm rev. 0 adf7011 ? register maps rf n register mo dulation register f unction register rf r register f1 r1 11-bit frequency error correction 4-bit r-value db19 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 clk out cl4 xoe reserved c2 (0) c1 (0) control bits db1 db0 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 r2 r3 r4 x1 cl1 cl2 cl3 r1 r2 c2 (0) c1 (1) m1 m12 12-bit fractional-n 8-bit integer-n db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 n8 db20 db21 db23 db22 vco band ld precision m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 n1 n2 n3 n4 n5 n6 n7 v1 ldp db16 db15 db14 db17 db20 db19 db18 db21 c2 (1) c1 (0) mo dulation deviation m odulation s cheme db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 po wer amplifier db22 db23 i ndex co unter gfsk mod cont rol pre- scaler p1 p5 p6 p7 s1 s2 p1 p2 p3 p4 d1 d2 d3 d4 d5 d6 d7 mc1 mc2 mc3 ic1 ic2 muxout m2 m1 pd1 t est modes c2 (1) c1 (1) db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db15 db14 db13 db12 db11 i1 data in vert db16 pd3 pll e nable clk out e nable pa e nable ch arge pump fast lock db17 db22 db21 db20 db19 db23 vco dis able db18 pd2 cp1 cp2 cp3 cp4 vp1 m3 m4 t1 t2 t3 t4 t5 t6 t7 t8 t9 db18 db20 db21 db22 db23 control bits control bits control bits rev. 0 e10e adf7011 rf r register 0 ........... 1 1 1 1023 0 ........... 1 1 0 1022 0 ........... . . . . 0 ........... 0 0 1 1 0 ........... 0 0 0 0 e.g., f-counter offset = 1, fractional offset = 1/2 15 f-counter offset f1 f2 f3 f11 ............................................................................................................................... .......................... 1 ........... 1 1 1 1 1 ........... 1 1 0 2 ........... . . . . 1 ........... 0 0 1 1023 1 ........... 0 0 0 1024 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 . . . . . . . . . . . . . . . 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15 r4 r3 r2 r1 rf r counter divide ratio 0 xtal oscillator on 1 xtal oscillator off x1 xoe eo eeeooeo e o xoe eee oo x o rev. 0 adf7011 ?1 rf n register c2 (0) c1 (1) m1 m12 c ontrol bits 12-bit fractional-n 8-bit integer-n db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 n8 db20 db21 db23 db22 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 n1 n2 n3 n4 n5 n6 n7 v1 ldp the n value chosen is a minimum of p 2 + 3p + 3. for prescaler = 8/9, this means a minimum n divide of 91. n counter divide ratio 0 0011111 31 0 0100000 32 0 0100001 33 0 0100010 34 . ....... . . ....... . . ....... . 1 1111101 253 1 1111110 254 1 1111111 255 n8 n7 n6 n5 n4 n3 n2 n1 modulus divide ratio 0 0 0 .......... 1 0 0 4 0 0 0 .......... 1 0 1 5 0 0 0 .......... 1 1 0 6 . . . .......... ... . . . . .......... ... . . . . .......... ... . 1 1 1 .......... 1 0 0 4092 1 1 1 .......... 1 0 1 4093 1 1 1 .......... 1 1 0 4094 1 1 1 .......... 1 1 1 4095 m12 m11 m10 .......... m3 m2 m1 vco band (mhz) 0 866?70 1 433?35 lock detect precision 0 3 cycles < 15ns 1 5 cycles < 15ns e.g., setting f = 0 in fsk mode turns on the - while the pll is an integer value e.g., modulus divide ratio = 2048 ? fraction 1/2 ldp v1 vco band ld precision rev. 0 e12e adf7011 modulation register d7 d6 . d2 d1 p7 p6 . p2 p1 d7. . . . d3 d2 d1 f deviation if frequency shift keying selected 0 . . . . 0 0 0 pll mode 0 . . . . 0 0 1 1 f step 0 . . . . 0 1 0 2 f step 0 . . . . 0 1 1 3 f step . . . . ............... 1 . . . . 1 1 1 127 f step d7 d3 d2 d1 divider factor 00 0 00 00 0 11 00 1 02 00 1 1 3 .. .. ...... 11 1 1 127 index counter 0 0 16 0 1 32 1 0 64 1 1 128 gfsk mod c ontrol 0 0 0 0 0 0 1 1 . . . . 1 1 1 7 modulation scheme 0 0 fsk 0 1 gfsk 1 0 ask 1 1 ook s2 s1 0 4/5 1 8/9 f step = f pfd /2 12 db16 db15 db14 db17 db20 db19 db18 db21 c2 (1) c1 (0) m odulation deviation db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 p ower amplifier db22 db23 i ndex c ounter gfsk mod c ontrol p1 p5 p6 p7 s1 c ontrol bits s2 p1 p2 p3 p4 d1 d2 d3 d4 d5 d6 d7 mc1 mc2 mc3 ic1 ic2 p1 rf prescaler mc3 mc2 mc1 ic2 ic1 power amplifier output level if amplitude shift keying selected, txdata = 0 if gaussian frequency shift keying selected pre- s caler modula tion s chem e 00.x xp a off 01.0 0 16.0dbm 01.0 1 16 1 (10/32) .... .. 01.1 1 16 31 (10/32) 10.0 0 6dbm 10.0 1 6 1 (10/32) .... .. 10.1 1 6 1 (10/32) 11.0 02dbm 11.0 12 1 (10/32) 11.. .. 11.1 1 12dbm 00.x xp a off 01.0 0 16.0dbm 01.0 1 16 1 (10/32) .... .. 01.1 1 16 31 (10/32) 10.0 0 6dbm 10.0 1 6 1 (10/32) .... .. 10.1 1 6 1 (10/32) 11.0 02dbm 11.0 12 1 (10/32) 11.. .. 11.1 1 12dbm rev. 0 adf7011 e13e function register m4 m3 m2 m1 muxout 0 0 0 0 logic low 0 0 0 1 logic high 0 0 1 0 three-state 0 0 1 1 regulator ready (default) 0 1 0 0 digital lock detect 0 1 0 1 analog lock detect 0 1 1 0 r divider / 2 output 0 1 1 1 n divider / 2 output 1 0 0 0 rf r divider output 1 0 0 1 rf n divider output 1 0 1 0 data rate 1 0 1 1 logic low 1 1 0 0 logic low 1 1 0 1 logic low 1 1 1 0 normal test modes 1 1 1 1 rev. 0 ?4 adf7011 default values for registers c2 (0) c1 (1) 0 1 c ontrol bits 12-bit fractional-n 8-bit integer-n db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 1 db20 db21 db23 db22 vco b and ld precis ion n register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mo dulation register db16 db15 db14 db17 db20 db19 db18 db21 c2 (1) c1 (0) m odulation deviation m odulation s cheme db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 p ower amplifier db22 db23 i ndex c ounter gfsk mod c ontrol pre- scaler 1 0 1 1 0 c ontrol bits 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f unction register muxout 1 1 0 t est modes c2 (1) c1 (1) db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db15 db14 db13 db12 db11 0 d ata in vert db16 1 pll enab le clk out e nable pa e nable c harge pump fast lock db17 db22 db21 db20 db19 db23 vco dis able c ontrol bits db18 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 11-bit frequency error correction 4-bit r-value db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 clk out db20 db19 1 xoe db21 db23 db22 r eserved c2 (0) c1 (0) c ontrol bits db1 db0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r register rev. 0 adf7011 e15e circuit description reference input section the on-board crystal oscillator circuitry (figure 2), allows the use of an inexpensive quartz crystal as the pll reference. the oscillator circuit is enabled by setting xoe e e xoxoo o xoe ooe o e e o x oo e o o o o o o o o o e o e o e e o o o p/p + 1) divides the rf signal from the vco to a lower frequency that is manageable by the cmos counters. the pfd takes inputs from the r counter and the n counter ( n = int + fraction ) and produces an output proportional to the phase and frequency difference between them. figure 4 is a simplified schematic. cp delay element u3 up charge pump cp gnd v p n divider hi d2 q2 clr2 u2 down hi d1 q1 clr1 u1 r divider r divider n divider cp output figure 4. pfd stage the pfd includes a delay element that sets the width of the antibacklash pulse. the typical value for this in the adf7011 is 3 ns. this pulse ensures that there is no dead zone in the pfd transfer function and minimizes phase noise and reference spurs. muxout and lock detect the muxout pin allows the user to access various internal points in the adf7011. the state of muxout is controlled by bits m1 to m4 in the function register. regulator ready this is the default setting on muxout after the transmitter has been powered up. the power-up time of the regulator is typically 50 s. since the serial interface is powered from the regulator, it is necessary for the regulator to be at its nominal voltage before the adf7011 can be programmed. the status of the regulator can be monitored at muxout. once the regulator ready signal on muxout is high, programming of the adf7011 may begin. rev. 0 ?6 adf7011 digital lock detect digital lock detect is active high. the lock detect circuit is con- tained at the pfd. when the phase error on five consecutive cycles is less than 15 ns, lock detect is set high. lock detect remains high until 25 ns phase error is detected at the pfd. since no external components are needed for digital lock detect, it is more widely used than analog lock detect. analog lock detect this n-channel open-drain lock detect should be operated with an external pull-up resistor of 10 k ? nominal. when lock has been detected, this output will be high with narrow low-going pulses. voltage regulator the adf7011 requires a stable voltage source for the vco and modulation blocks. the on-board regulator provides 2.2 v using a band gap reference. a 2.2 f capacitor from c reg to ground is used to improve stability of the regulator over a sup- ply ranging from 2.3 v to 3.6 v. the regulator consumes less than 400 a and can only be powered down using the chip enable (ce) pin. bringing ce low disables the regulator and also erases all values held in the registers. the serial interface operates off the regulator supply; therefore, to write to the part, the user must have ce high. regulator status can be monitored using the regulator ready signal from muxout. loop filter the loop filter integrates the current pulses from the charge pump to form a voltage that tunes the output of the vco to the desired frequency. it also attenuates spurious levels generated by the pll. a typical loop filter design is shown in figure 6. c harge pump out vco figure 6. typical loop filter configurationthird order integrator in fsk, the loop should be designed so that the loop bandwidth (lbw) is approximately five times the data rate. widening the lbw excessively reduces the time spent jumping between frequencies but may cause insufficient spurious attenuation. for ask systems, the wider the loop bw the better. the sud- den large transition between two power levels will result in vco pulling and can cause a wider output spectrum than is desired. by widening the loop bw to >10 times the data rate, the am ount of the vco pulling is reduced since the loop will quickly settle back to the correct frequency. the wider lbw may restrict the output power and data rate of ask based systems, compared with fsk based systems. narrow-loop bandwidths may result in the loop taking long periods of time to attain lock. careful design of the loop filter is critical in obtaining accurate fsk/gfsk modulation. for gfsk, it is recommended that an lbw of 2.0 to 2.5 times the data rate be used to ensure sufficient samples are taken of the input data while filtering system noise. re gulator ready d igital lock detect a nalog lock detect r counter/2 output n counter/2 output r counter output n counter output mux control muxout dgnd dv dd figure 5. muxout stage rev. 0 adf7011 e17e voltage controlled oscillator (vco) an on-chip vco is included on the transmitter. the vco con- verts the control voltage generated by the loop filter into an output f requency that is sent to the antenna via the power amplifier (pa). the vco has a typical gain of 80 mhz/v and operates from 866 mhz to 870 mhz. the pd1 bit in the function regis- ter is the active high bit that turns on the vco. a frequency divided by 2 is included to allow operation in the lower 450 mhz band. to enable operation in the lower band, the v1 bit in the n register should be set to 1. the vco needs an external 220 nf between the vco and the regulator to reduce internal noise. mux vco select bit to pa and n divider divide by 2 vco control bit loop filter c reg pin 220nf vco figure 7. voltage controlled oscillator rf output stage the rf output stage consists of a dac with a number of cur- rent sources to adjust the output power level. to set up the power level ? fsk gfsk: the output power is set using the modulation register by entering a 7-bit number into bits p1ep7. the two msbs set the range of the output stage, while the five lsbs set the output power in the selected range. ? ask: the output power as set up for fsk is the output power for a txdata of 1. the output power for a zero data bit is set up the same way but using bits d1ed7. the output stage is powered down by setting bit pd2 in the function register to zero. p5 p1 p7, p6 high med low figure 8. output stage serial interface the serial interface allows the user to program the four 24-bit registers using a 3-wire interface (clk, data, and load enable). the serial interface consists of a level shifter, a 24-bit shift regis- ter, and four latches. signals should be cmos compatible. the serial interface is powered by the regulator, and therefore is inactive when ce is low. table i. c2, c1 truth table c2 c1 data latch 00 r register 01 n register 10 modulation register 11 function register data is clocked into the shift register, msb first, on the rising edge of each clock (clk). data is transferred to one of four latches on the rising edge of le. the destination latch is deter- mined by the value of the two control bits (c2 and c1). these are the two lsbs, db1 and db0, as shown in the timing dia- gram of figure 1. v dd rf out pa l1 c1 50 l2 figure 9. output stage matching rev. 0 e18e adf7011 16 e j33 868mhz 5.00 1.00 0.50 0.20 0.00 0.0 0.20 0.50 1.00 2.00 30 40 50 60 70 80 90 100 110 120 130 140 150 2.00 5.00 25 e j2.6 433mhz figure 10. output impedance on smith chart fractional-n n counter and error correction the adf7011 consists of a 15-bit pfd frequency int fractional error + () + 8 2 15 integer-n fractional-n r reference in n third order - modulator pfd/ charge pump vco figure 11. fractional-n pll fractional-n registers the fractional part is made up of a 15-bit divide, made up of a 12-bit n value in the n register summed with a 10-bit value (plus sign bit) in the r register that is used for error correction, as shown in figure 12. m12 m11 m10 m9 m8 m 7m6m5m4m3m2m1 12-bit n value f10 f9 f8 f 7f6f5f4 10-bit ( sign) error correction f3 f2 f1 n14 n13 n12 n11 n10 n9 n8 n7 n6 n5 n4 n3 15-bit fractional n register n2 n1 n0 figure 12. fractional components the resolution of each register is the smallest amount that the output frequency can be changed by changing the lsb of the register. changing the output frequency the fractional part of the n register changes the output fre- quency by pfd frequency fractional gister value re 2 12 the frequency error correction contained in the r register changes the output frequency by pfd frequency error correction gister value re 2 15 by default, this will be set to 0. the user can calibrate the system and set this by writing a twos complement number to bits f1ef11 in the r register. this can be used to compensate for initial error, temperature drift, and aging effects in the crystal reference. integer-n register the integer part of the n counter contains the prescaler and a and b counters. it is eight bits wide and offers a divide of p 2 + 3p + 3 to 255. the combination of the integer (255) and the fractional (31767/ 31768) gives a maximum n divider of 256. the minimum us able pfd is maximum quired output frequency re 255 1 + () for use in the european 868 mhz to 870 mhz band, there is a restriction to using a minimum pfd of 3.4 mhz to allow the user to have a center frequency of 870 mhz. pfd frequency the pfd frequency is the number of times a comparison is made between the reference frequency and the feedback signal from the output. the higher the pfd frequency, the more often a comparison is made at the pfd. t his means that the frequency lock time will be reduced when jumping from one frequency to another by increasing the pfd. having a pfd of > 5 mhz will reduce the available output power due to en300-220 spurious regulations. rev. 0 adf7011 ?9 modulation schemes frequency shift keying (fsk) frequency shift keying is implemented by setting the n value for the center frequency and then toggling this with the tx data line. the deviation from the center frequency is set using bits d1?7 in the modulation register. the deviation from the center frequency in hz is fsk hz pfd frequency modulation number deviation () = 2 12 the modulation number is a number from 1 to 127 (bits d1 d7 in modulation register). fsk is selected by setting bits s1 and s2 to zero in the modulation register. r pfd/ charge pump integer-n fractional-n third order - modulator ? dev +f dev txdata fsk deviation frequency internal vco using spiral inductors gain 70 mhz/v?0 mhz/v pa stage cheap at crystal vco figure 13. fsk implementation gaussian frequency shift keying (gfsk) gaussian frequency shift keying reduces the bandwidth occu pied by the transmitted spectrum by digitally prefiltering the tx data. a txclk output line is provided from the adf7011 for syn- chronization of txdata from the microcontroller. the txclk line may be connected to the clock input of an external shift register that clocks data to the transmitter at exact data rate. shift register adf7011 data from microcontroller txdata txclk antenna figure 14. txclk pin synchronizing data for gfsk setting up the adf7011 for gfsk to set up the frequency deviation, set the pfd and the mod control bits mc1 to mc3. gfsk hz pfd frequency deviation m () = 2 2 12 where m is mod control (bits mc1 to mc3 in the modulation register). to set up the gfsk data rate data rate bits s pfd frequency divider factor index counter / () = amplitude shift keying (ask) amplitude shift keying is implemented by switching the output stage between two discrete power levels. this is implemented by toggling the dac, which controls the output level between two 7-bit values set up in the modulation register. a zero txdata bit sends bits d1?7 to the dac. a high txdata bit sends bits p1?7 to the dac. a maximum modulation depth of 30 db is possible. ask is selected by setting bit s2 = 1 and bit s1 = 0. on-off keying (ook) on-off keying is implemented by switching the output stage to a certain power level for a high txdata bit and switching the output stage off for a zero. due to feedthrough effects, a maximum modulation depth of 33 db is specified. for ook, the transmitted power for a high input is programmed using bits p1?7 in the modulation register. ook is selected by setting bits s1 and s2 to 1 in the modulation register. choosing channels for best system performance the fractional-n pll allows the selection of any channel within 868 mhz to 870 mhz to a resolution of rev. 0 e20e adf7011 application examples application example 1 operating frequency 433.92 mhz output power +10 dbm current consumption <30 ma modulation ask/fsk this system should be set up as shown figure 15. the spurious levels using a crystal frequency of 4 mhz are sufficiently low so as not to require any band-pass filtering of the output. however, 2 db of attenuation will be required at 541.50 mhz in order to comply with es-300-220. this can be achieved easily with the harmonic filter. the harmonic filter can be designed at the output of the matching network with 50 impedance, or it may be integrated into the matching network. the adf7011 will allow multichannel operation in the 433 mhz band. if fsk modulation is used, the bw should be about five times the data rate. in the case of ask modulation, a minimum data rate of 1 mhz should be used to minimize the occupied spectrum. the free design tool, adisimpll, should be down- loaded from www.analog.com/pll to ascertain the values of the filter components. application example 2 operating frequency 868.3 mhz output power +3 dbm current consumption <25 ma modulation ask/fsk in order to meet the etsi requirement en300-220, the maxi- mum output power without using a filter is +3 dbm. this is because the spurious levels scale with output power. utilizing a pfd frequency of 4.42 mhz will reduce the level of the refer- ence spurs, and place the first spur in a e36 dbm bin, 4.4 mhz below the carrier. adisimpll should be used to design the loop filter, aiming for a loop bandwidth of five times the data rate for fsk. ask modulation requires a loop bw > 1 mhz to minimize spectral occupancy. application example 3 operating frequency 868.3 mhz output power +10 dbm current consumption <40 ma modulation ask/fsk in order to meet the etsi requirements at +10 dbm output power, it is necessary to add an inexpensive gigafilt from murata at the output. this will reduce the prescaler and refer- ence spurious levels to e54 dbm, and also reduce the harmonic levels to within the e30 dbm level. given that the insertion loss is 2 db, it is necessary to use the maximum +12 dbm power from the adf7011 to achieve an antenna port level of +10 dbm. the filter layout is important to ensure that there is margin in the output spectrum; filter data sheet guidelines should be adhered to. rev. 0 adf7011 e21e 12nh 6.8nh 10pf 3.9pf cpv dd dv dd rf out r set 4.7k c reg 2.2 f 220nf c vco cp out vco in vco in le clk data ce txdata l ock detect 2mh z cl ock mux out clk out 4mhz 33pf 33pf test gnd osc2 osc1 50 lc filter adf7011 decoupling capacitors have been omitted for clarity. figure 15. application diagram?433 mhz operation with +10 dbm output power 12nh 6.8nh 10pf cpv dd dv dd rf out r set 4.7k c reg 2.2 f 220nf c vco cp out vco in vco in le clk data ce txdata l ock detect 4.84mh z cl ock mux out clk out 22.1184mhz 33pf 33pf test gnd osc2 osc1 50 adf7011 decoupling capacitors have been omitted for clarity. r = 5 figure 16. application diagram?868 mhz operation with +3 dbm output power rev. 0 e22e adf7011 12nh 6.8nh 10pf cpv dd dv dd rf out r set 4.7k c reg 2.2 f 220nf c vco cp out vco in vco in le clk data ce txdata l ock detect 4.84mh z cl ock mux out clk out 22.1184mhz 33pf 33pf test gnd osc2 osc1 50 adf7011 decoupling capacitors have been omitted for clarity. r = 5 murata gigafilt dfcb2869mlejaa-tt1 figure 17. application diagram?868 mhz operation with +10 dbm output power rev. 0 adf7011 e23e outline dimensions 24-lead thin shrink small outline package [tssop] (ru-24) dimensions shown in millimeters 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane compliant to jedec standards mo-153ad 0.10 coplanarity c03770e0e6/03(0) e24e |
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